This invention is in the field of solid-state memory as realized in semiconductor integrated circuits. Embodiments of this invention are more specifically directed to the use of redundant memory cells to functionally replace defective memory cells in such memories.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Many of these electronic devices and systems are now portable or handheld devices. For example, many mobile devices with significant computational capability are now available in the market, including modern mobile telephone handsets such as those commonly referred to as “smartphones”, personal digital assistants (PDAs), mobile Internet devices, tablet-based personal computers, handheld scanners and data collectors, personal navigation devices, and the like. The power consumption of the electronic circuitry in those devices and systems is therefore of great concern, as battery life is often a significant factor in the buying decision as well as in the utility of the device or system. One type of mobile devices includes implantable battery-powered medical devices, such as pacemakers, defibrillators, and the like. Battery life is of special concern in these implantable medical devices, because surgery is required to replace the battery.
Many mobile devices, including implantable medical devices, now rely on solid-state memory not only for data storage during operation, but also as non-volatile memory for storing program instructions (e.g., firmware) and for storing the results and history of previous operations and calculations. Electrically-erasable programmable read-only memory (EEPROM) is a common type of solid-state non-volatile memory, particularly EEPROM of the “flash” type. Ferroelectric random-access memory (FeRAM or FRAM) is a popular non-volatile solid-state memory technology, particularly in implantable medical devices. Modern mobile devices typically include substantial non-volatile memory capacity, often amounting to as much as one or more gigabytes.
A continuing trend in the industry, particularly as applied to mobile devices including implantable medical devices, is to realize as many system functions as possible in a single integrated circuit. As such, large-scale integrated circuits now often include one or more central processing units (CPUs), co-processor functions as desired, one or more memory resources embedded on-chip for use as program and data memory, and various input/output and control functions. Examples of these large-scale integrated circuits are often referred to as a single-chip microcomputer, or a so-called “system-on-a-chip” (SoC).
The miniaturization of these integrated circuit functions is an important design goal, whether to minimize manufacturing cost or to provide a minimum form factor. Given the substantial memory capacity now required by these computationally sophisticated, a significant portion of the overall chip area is consumed in realizing solid-state memory, particularly non-volatile solid-state memory, even in large-scale SoC implementations. As such, memory cells are often realized by minimum size transistor gates and other features, considering the relatively large number of memory cells in even modest-sized memories. The manufacturing yield of modern SoC integrated circuits is thus often dominated by manufacturing defects in the memory arrays, considering that a relatively large portion of the overall chip area is consumed by the memory arrays, and that the memory arrays are constructed of a large number of closely-packed, minimum feature size, memory cells. A defective embedded on-chip memory causes the entire SoC to be unsuitable for system use, regardless of the functionality of the remainder of the integrated circuit.
As known in the art, yield loss due to memory defects can be alleviated by the use of redundant rows or columns (or both) of memory cells associated with the memory arrays. In a general sense, if one or more memory cells in the memory array fails electrical test, the memory is remapped to access a redundant row or column of memory cells instead of the row or column of the main array containing the defective cell or cells. To the outside, the memory appears to have all cells fully functional.
U.S. Patent Application Publication No. US 2010/0211853 A1, published Aug. 19, 2010, entitled “High Reliability and Low Power Redundancy for Memory”, commonly assigned herewith and incorporated herein by this reference, describes a memory architecture with an FeRAM main array and a redundancy circuit. This publication discloses an example in which the redundancy circuit includes a static random access memory (SRAM) that stores the memory addresses to be replaced in each of multiple array segments, along with a repair enable bit that enables selection of the redundant row or column upon the redundant address matching the address of the desired memory location. A portion of FeRAM is provided for non-volatile storage of the redundant address and enable information; upon power-up, the contents of that FeRAM portion are written into the SRAM redundancy memory; the use of SRAM memory allows the redundancy decision to be made within the memory access cycle itself.
As mentioned above, power consumption of integrated circuit functions is an important concern in the design and manufacture of mobile electronic devices and systems, especially for implantable medical devices. It has been observed, however, that significant power remains being consumed by the SRAM redundancy memory, considering that this memory has at least one data word for each segment of the non-volatile array.